1. Field of the Invention
The present invention relates to flash memory technology, and more particularly to methods for erasing charge trapping memory cells having dielectric charge trapping structures.
2. Description of Related Art
Flash memory is a class of non-volatile integrated circuit memory technology. Traditional flash memory employs floating gate memory cells storing charge on an electrically conductive layer between the channel and gate of a transistor. The charge stored affects the threshold voltage of the transistor, and the threshold voltage of the transistor due to the stored charge can be sensed to indicate data.
As the density of floating gate memory cells increases, interference between the charge stored on adjacent floating gates limits the ability to increase the density of floating gate based memory.
Another type of memory cell based on storing charge between the channel and gate of a transistor uses a dielectric charge trapping structure to store charge. Dielectric charge trapping memory cells do not cause cell-to-cell interference like that encountered with floating gate technology, and thus are expected to be implemented in higher density flash memory.
In dielectric charge trapping memory cells, a dielectric charge storage layer is formed over a tunneling dielectric which isolates the charge storage layer from a channel region of a semiconductor substrate, and a blocking dielectric layer is formed over the charge storage layer to isolate it from a gate. A representative device is known as a silicon-oxide-nitride-oxide-silicon SONOS cell.
SONOS-type devices can be programmed by tunneling of electrons into the charge storage layer using one of a number of well-known biasing techniques (for example, Fowler Nordheim (FN) tunneling, Channel Hot Electron (CHE), etc).
SONOS-type devices can be erased by hole tunneling into the charge storage layer or by electron de-trapping from the charge storage layer. Since electrons in the dielectric charge storage layer are not free to move, hole tunneling may be preferred in order to achieve practical erase operation speeds.
During erase, injection of electrons from the gate into the dielectric charge storage layer results in an erase saturation condition in which the charge in the charge storage layer converges to an equilibrium level, thus limiting the minimum threshold voltage of the memory cell. See, U.S. Pat. No. 7,075,828, entitled “Operation Scheme with Charge Balancing Erase for Charge Trapping Non-Volatile Memory”, invented by Lue et al.
It is desirable to obtain low erase threshold voltages, particularly for memory cells arranged in a NAND array, because it allows for lower voltage operations of the memory cell during read and program operations. Additionally, if the erased threshold voltage is too high the memory window between the programmed and erased threshold states may become too small for many applications.
Conventional biasing techniques for achieving a lower erase threshold voltage result in a slower erase speed since a lower magnitude voltage between the gate and channel of the memory cell must be applied.
Other techniques for achieving lower erase threshold voltage memory cells include reducing the injection of electrons from the gate by employing a high work function gate material and/or a high dielectric constant material in the blocking dielectric layer. However, the problem of erase saturation continues to limit performance of dielectric charge trapping memory cells.
Accordingly, it is desirable to provide efficient methods for erasing dielectric charge trapping memory cells which address the erase saturation issues and result in lower erase threshold voltages.